1. Technical Field
The present invention relates to a non-volatile memory circuit (also referred to below as PROM) that employs zener zap devices (also referred to below as ZapFuses) and to a semiconductor device and reading method thereof. The present invention particularly relates to a non-volatile memory suitable for achieving increased capacities without causing a drop in reading speed, and to a semiconductor device of the same.
2. Related Art
As disclosed in for example Japanese Patent Application Laid-Open (JP-A) No. 2003-204069, in a zener zap device with a zap diode configured by forming a P-type well region to a surface layer of an N-type semiconductor layer, forming a P-type anode region and an N-type cathode region in the P-type well region, and with the P-type anode region and the N-type cathode region respectively connected through an anode electrode and a cathode electrode, the PN junction is broken down by applying a reverse bias voltage of a breakdown voltage or greater to the zap diode so as to short between the anode electrode and the cathode electrode and act as a resistor.
A PROM circuit employing zener zap devices as storage units for single bits operates in a data write mode that zaps the zener zap devices for each bit, and in a read mode that reads the written data. In the read mode, a method and a circuit configuration is employed in which a current is applied to each of the zener zap devices for every bit, and the data of each bit is read to be transmitted to an operation circuit.
For example JP-A No. 2005-182899, discloses a PROM circuit including: plural memory devices (zener zap devices) each having one end connected to a common write current input terminal and the other end connected to respective read terminals; plural ON/OFF state controllable switch elements (transistors) each having one end connected to the respective read terminal and the other end connected to a common reference voltage terminal; plural current sources respectively connected between the plural read terminals and the reference voltage terminal; and a diode having one end connected to the write current input terminal and the other end connected to a voltage source, with the diode connected in a direction so as to prevent a write current during writing from flowing to the voltage source. The PROM circuit is configured such that when selectively writing to the memory devices, the switch elements are selectively placed in an ON state, and changes in the resistance values of the memory devices are selectively induced by a current flowing from the write current input terminal and into a write current absorption terminal When data written to the memory devices is read, all of the plural switch elements are placed in an OFF state, and a rise or fall in voltage with respect to the reference voltage terminal is induced in the plural read terminals (P2 to P3) due to differences in voltage fall occurring in the respective memory devices due to current flowing from the voltage source, through the diode and the plural memory devices, to the plural current sources.
According to the PROM circuit of JP-A No. 2005-182899, the previous need to provide an interference prevention diode to each of the PROM devices is eliminated, and a single switch suffices for devices over a large area. The surface area occupied in an IC can accordingly be reduced. Moreover, even should a large voltage occur at both ends of a PROM device during writing, the voltage applied to the switch elements for selective writing is low, and so there is no need to employ an element with a high withstand voltage. Moreover, the terminal potential of the selective writing switch elements increases due to the voltages arising at both ends of the PROM circuit, enabling difficulties in switch element control and inability to make sufficient write current flow to be resolved.
However, in the PROM circuit of JP-A No. 2005-182899, there is a need to form a Thick A1 filament line in the zener zap devices to apply a constant zap current in the region of 150 mA to 200 mA such that the A1 filament line does not break when a read current flows during normal circuit operation.
As a result, there is the issue of an increase in cell size due to provision of the transistor for applying the zap current of 150 mA to 200 mA and the inflow prevention diode. In particular, the chip surface area of the product increases the higher the number of bits and the larger the surface area occupancy ratio of the PROM circuit.
JP-A No. 2007-265540 discloses a PROM circuit directed towards resolving such issues. The PROM circuit of JP-A No. 2007-265540 is configured including, for each single zener zap device: a diode that prevents inflow to another bit in a normal mode; a diode to protect a circuit on an output terminal side; a first transistor that selects the zener zap device and applies a zap current during writing; a second transistor that serves as a switch element controlling a read current; a resistor that causes a voltage fall during reading; and a latch circuit that holds data read through the zener zap device during read mode.
Such a configuration enables prolonged use even with a fine A1 filament zapped with a low current critical for zapping, enabling a reduction in cell size to be achieved. It is accordingly possible to provide a zener zap PROM circuit with reduced chip size.
For PROM circuits employing zener zap devices as storage units for single bits, various known technology is proposed, such as for example disclosed in JP-A No. 2003-204069, that enables economical electrical writing on a small-scale and features high reliability after writing, and also avoids an increase in surface area accompanying increasing capacities of PROM circuits.
However, in the technology of for example JP-A No. 2007-265540, the latch circuits and inflow prevention diodes etc. are provided for each storage unit, leading to an increase in layout surface area when the number of storage units is increased in order to achieve increased capacity.
Moreover, in each of the related technologies, a write power supply and a read power supply are each separately provided, and moreover the read power supply is configured for each of the storage units, leading to an increase in layout surface area when the number of storage units is increased in order to achieve increased capacity.
Moreover, in each of the related technologies, in PROM circuits configured to serially read the output of the storage units, namely PROM circuits configured to increase capacity with the cathodes of the zener zap devices (ZapFuse) commonly connected and only the zener zap devices and transistors for selecting the anode of the zener zap devices connected in parallel, no consideration is given to the voltage swing of the cathodes of the zener zap devices detected during data reading. In such PROM circuits configured to serially read the output of the storage units, when the number of storage units is increased to achieve increased capacity, an increase in read time occurs accompanying the increase in capacity of cathodes, with the issue of decreased read speed.
Accordingly, in the related technology, and in particular in PROM circuits configured to serially read the output of the storage units, an increase in surface area and an increase in read time is unavoidable when the number of storage units is increased to achieved increased capacity.